FE3000 used in Commodore and Amiga equipment

IC number: FE3000
IC function: CPU controller
Related components: FE3010, FE3020, FE3030 (rest of chipset), 80286 (processor)

Component documentation
IC number	Manufacturer	Documentation
FE3000	Faraday	Not available

Component versions
IC number	Package	CBM part number	CBM part description
FE3000A	84-pin PLCC	390316-01	FE3000A

Positions
Device	Positions	Package
A2286 main board	U3	PLCC
PC30-III	U801	PLCC
PC40-III	U801	PLCC

Pinout
Pin	Type	Name	Description
1	Power	VSS	GROUND
2	I/O	NXBHE	BUS HIGH ENABLE
3	I/O	NYIOR	I/O READ COMMAND
4	I/O	NYIOW	I/O WRITE COMMAND
5	I/O	NYMEMR	MEMORY READ COMMAND
6	I/O	NUMEMW	MEMORY WRITE COMMAND
7	Output	AIOW	EXTENDED I/O WRITE COMMAND
8	Output	AS	REAL TIME CLOCK ALE
9	Output	BALE	BUS ADDRESS LATCH ENABLE
10	Output	CPUHRQ	BUS HOLD REQUEST TO 80286
11	Output	CTLOFF	DATA LATCH CONTROL
12	Output	DMARDY	READY TO DMA
13	Output	DMACLK	CLOCK TO DMA DEVICES
14..15	Input	A0..A1	80286 ADDRESS A0..A1
16	Input	EAIOCK	ENABLE I/O CHECK
17	Input	EMBRMCK	ENABLE RAM PARITY CHECK CONTROL
18	Input	ENPAL2	ENABLE EXTERNAL WAIT STATE
19	Input	F16	16 BIT MEMORY OPERATION
20	Input	HLDA	HOLD ACKNOWLEDGE FROM THE 80286
21	Input	HRQ1	HOLD REQUEST
22	Input	IOCRDY	EXPANSION BUS READY
23..24	Input	MDPIN0..MDPIN1	PARITY BIT FROM RAM BANK0..1
25	Input	MNIO	MEMORY I/O SELECT
26..27	Input	NAEN1..NAEN2	ENABLE DMA CHANNELS 0-3..5-7 TO USE DATA BUS
28	Input	NBUSY	BUSY STATUS ASSERTED BY 80287
29	Input	NCS287	80287 I/O CHIP DECODE
30	Output	NIRQ13	INTERRUPT REQUEST 13
31	Input	NDMAMR	DMA MEMORY READ COMMAND
32	Output	RST287	RESET TO 80287
33	Output	SYSCLK	SYSTEM CLOCK
34	Output	RESCPU	RESET TO 80286
35	Output	REFDET	REFRESH DETECT
36	Output	Q1	START OF BUS CYCLE
37	Output	PCK	PARITY CHECK
38	Output	PCLK	CLOCK TO 8042
39	Output	PROCLK	PROCESSOR CLOCK TO 80286
40	Output	NPCLK	INVERTED CLOCK TO 8042
41	I/O	NRFSH	REFRESH CYCLE
42	Power	VSS	GROUND
43	Power	VDD	+5 VOLTS SUPPLY
44	I/O	XA0	ADDRESS A0
45..46	Output	NDEN0..NDEN1	GATE DATA 0-7..8-15
47	Output	DIR245	BYTE SWAP DIRECTION
48	Output	NERFSH	ENABLE REFRESH ADDRESS
49	Output	NNPCS	80287 CHIP SELECT
50	Output	NEDMMR	ENABLE DMA MEMORY READ
51	Output	NINTA	INTERRUPT ACKNOWLEDGE
52	Output	NNMI	NMI OUTPUT TO 80286
53	Output	NBZ286	80287 BUSY TO 80286
54	Output	LSA0	LATCHED SYSTEM ADDRESS A0
55	Output	IOCHCK	I/O DEVICE ERROR
56	N/C	UNUSED	UNUSED
57	Input	NERROR	80287 ERROR
58	Input	NIOCHK	I/O CHECK
59	Input	NIOS16	16 BIT I/O TRANSFER
60	Input	NNMICS	NMI PORT DECODE
61	Input	NRAMSL	ON BOARD RAM DECODE
62	Input	NRESIN	RESET IN
63	Input	NENFAST	ENABLE LOOK AHEAD DECODE
64	Input	NZROWS	ZERO WAIT STATES
65	Input	OUT1	TERMINAL COUNT OF TIMER CHANNEL 1
66	Input	RC	RESET TO CPU 80286
67..68	Input	S0..S1	BUS CYCLE STATUS S0..S1 FROM 80286
69	Input	XA3	ADDRESS A3
70	Input	XD7	SYSTEM DATA BUS BIT 7
71	Input	NENDCY	TERMINATE CURRENT CYCLE
72	Output	HLDA1	HOLD ACKNOWLEDGE TO DMA
73	Output	F119M	1.19 MHz CLOCK TO TIMER
74	Output	F14M	14.318 MHz SIGNAL TO EXPANSION BUS
75	Output	GTE245	ENABLE BUS SWAP
76	Output	NRESET	RESET TO SYSTEM LOGIC
77	Output	NREADY	SYNCHRONIZED READY TO CPU
78	Input	X18284	CRYSTAL TO 8284 CLOCK GENERATOR
79	Output	X28284	CRYSTAL TO 8284 CLOCK GENERATOR
80	Input	X1284	CRYSTAL TO 82284 CLOCK GENERATOR
81	Output	X2284	CRYSTAL TO 82284 CLOCK GENERATOR
82	Output	DTNR	DATA DIRECTION CONTROL
83	Output	ALE	ADDRESS LATCH ENABLE
84	Power	VDD	+5 VOLTS SUPPLY