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Last update: 7 February 2004

IC number:FE3000
IC function:CPU controller
Related components:FE3010, FE3020, FE3030 (rest of chipset), 80286 (processor)

Component documentation
IC numberManufacturerDocumentation
FE3000FaradayNot available

Component versions
IC numberPackageCBM part numberCBM part description
FE3000A84-pin PLCC390316-01FE3000A

Positions
DevicePositionsPackage
A2286 main boardU3PLCC
PC30-IIIU801PLCC
PC40-IIIU801PLCC

Pinout
PinTypeNameDescription
1PowerVSSGROUND
2I/ONXBHEBUS HIGH ENABLE
3I/ONYIORI/O READ COMMAND
4I/ONYIOWI/O WRITE COMMAND
5I/ONYMEMRMEMORY READ COMMAND
6I/ONUMEMWMEMORY WRITE COMMAND
7OutputAIOWEXTENDED I/O WRITE COMMAND
8OutputASREAL TIME CLOCK ALE
9OutputBALEBUS ADDRESS LATCH ENABLE
10OutputCPUHRQBUS HOLD REQUEST TO 80286
11OutputCTLOFFDATA LATCH CONTROL
12OutputDMARDYREADY TO DMA
13OutputDMACLKCLOCK TO DMA DEVICES
14..15InputA0..A180286 ADDRESS A0..A1
16InputEAIOCKENABLE I/O CHECK
17InputEMBRMCKENABLE RAM PARITY CHECK CONTROL
18InputENPAL2ENABLE EXTERNAL WAIT STATE
19InputF1616 BIT MEMORY OPERATION
20InputHLDAHOLD ACKNOWLEDGE FROM THE 80286
21InputHRQ1HOLD REQUEST
22InputIOCRDYEXPANSION BUS READY
23..24InputMDPIN0..MDPIN1PARITY BIT FROM RAM BANK0..1
25InputMNIOMEMORY I/O SELECT
26..27InputNAEN1..NAEN2ENABLE DMA CHANNELS 0-3..5-7 TO USE DATA BUS
28InputNBUSYBUSY STATUS ASSERTED BY 80287
29InputNCS28780287 I/O CHIP DECODE
30OutputNIRQ13INTERRUPT REQUEST 13
31InputNDMAMRDMA MEMORY READ COMMAND
32OutputRST287RESET TO 80287
33OutputSYSCLKSYSTEM CLOCK
34OutputRESCPURESET TO 80286
35OutputREFDETREFRESH DETECT
36OutputQ1START OF BUS CYCLE
37OutputPCKPARITY CHECK
38OutputPCLKCLOCK TO 8042
39OutputPROCLKPROCESSOR CLOCK TO 80286
40OutputNPCLKINVERTED CLOCK TO 8042
41I/ONRFSHREFRESH CYCLE
42PowerVSSGROUND
43PowerVDD+5 VOLTS SUPPLY
44I/OXA0ADDRESS A0
45..46OutputNDEN0..NDEN1GATE DATA 0-7..8-15
47OutputDIR245BYTE SWAP DIRECTION
48OutputNERFSHENABLE REFRESH ADDRESS
49OutputNNPCS80287 CHIP SELECT
50OutputNEDMMRENABLE DMA MEMORY READ
51OutputNINTAINTERRUPT ACKNOWLEDGE
52OutputNNMINMI OUTPUT TO 80286
53OutputNBZ28680287 BUSY TO 80286
54OutputLSA0LATCHED SYSTEM ADDRESS A0
55OutputIOCHCKI/O DEVICE ERROR
56N/CUNUSEDUNUSED
57InputNERROR80287 ERROR
58InputNIOCHKI/O CHECK
59InputNIOS1616 BIT I/O TRANSFER
60InputNNMICSNMI PORT DECODE
61InputNRAMSLON BOARD RAM DECODE
62InputNRESINRESET IN
63InputNENFASTENABLE LOOK AHEAD DECODE
64InputNZROWSZERO WAIT STATES
65InputOUT1TERMINAL COUNT OF TIMER CHANNEL 1
66InputRCRESET TO CPU 80286
67..68InputS0..S1BUS CYCLE STATUS S0..S1 FROM 80286
69InputXA3ADDRESS A3
70InputXD7SYSTEM DATA BUS BIT 7
71InputNENDCYTERMINATE CURRENT CYCLE
72OutputHLDA1HOLD ACKNOWLEDGE TO DMA
73OutputF119M1.19 MHz CLOCK TO TIMER
74OutputF14M14.318 MHz SIGNAL TO EXPANSION BUS
75OutputGTE245ENABLE BUS SWAP
76OutputNRESETRESET TO SYSTEM LOGIC
77OutputNREADYSYNCHRONIZED READY TO CPU
78InputX18284CRYSTAL TO 8284 CLOCK GENERATOR
79OutputX28284CRYSTAL TO 8284 CLOCK GENERATOR
80InputX1284CRYSTAL TO 82284 CLOCK GENERATOR
81OutputX2284CRYSTAL TO 82284 CLOCK GENERATOR
82OutputDTNRDATA DIRECTION CONTROL
83OutputALEADDRESS LATCH ENABLE
84PowerVDD+5 VOLTS SUPPLY

Copyright © 2004 Ronald van Dijk - All rights reserved